FPGAs considered ARM-full

[Xilinx](http://www.xilinx.com) and [Altera](http://www.altera.com) have [both](http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1534041&highlight=) [announced](http://www.altera.com/corporate/news_room/releases/2011/products/nr-soc-fpga.html) FPGAs with hard [ARM](http://www.arm.com) processors on them. Xilinx have even got a new product famliy name (Zynq) for them.

Me: One, Tiny pieces of plastic: Nil

For want of a better place to log how to get at the dishwasher pump *next* time it gets stuck with a tiny piece of plastic blocking the impeller, I’m sticking it here.

In case it helps anyone else it’s a Bosch Classixx (no idea what model no, bought about 2004 IIRC). Here are the steps:

EEWeb electronic design site

I recently became aware of the [EEWeb](http://www.eeweb.com/) electronic design site (as one of their reps emailed me to see if I’d like my site to appear on their front page… we’ll see if my server can handle that soon!)

It’s sponsored by [Digikey](http://digikeycom/), much like [RS](http://rswww.com)’s [DesignSpark](http://www.designspark.com/) and [Farnell](http://uk.farnell.com/)’s [element14](http://element14.com).

There’s an awful lot of content and I’ve barely scratched through a tiny bit of it – worth a trawl!

libv has a home

Some of my “useful bits” of library code have lived in `libv.vhd` for a while – I’ve split it off and licensed it with a CC0 license (which means the author disclaims copyright and offers no warranty). It’s [on github](https://github.com/martinjthompson/libv) and I’ll add contributions from anyone who has any!

Either individual functions to add to libv.vhd or great big wodges of useful code (like Jim Lewis’ [randomized testing libraries](http://www.synthworks.com/downloads/index.htm) maybe….)

Should VHDL be extended to allow the use of Unicode

I’m contributing to the [VASG](http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome) group which is working on coming up with what the next revision of VHDL should be able to do.

On today’s conference call, the idea was mooted that VHDL could allow the use of Unicode identifiers (ie entity, signal, variable names etc.).

All of today’s participants were (as far as I recall) native English speakers without much call for accented characters, much less characters from entirely different writing systems. So I’m putting a call out to see if there’s any interest from the wider community in pushing forwards a requirement for VHDL compilers to support Unicode.

Feel free to [mail me](mailto:vhdl_unicode@parallelpoints.com), comment below or [@mention me in a tweet](http://twitter.com/martinjthompson) with your thoughts – I’ll summarise the results here in a few weeks

Variables and signals in VHDL – and when variables are better

VHDL has two types of what-would-normally-be-called-variables:

* `signal`s, which must be used for inter-process communication, and can be used for process-local storage
* `variable`s which are local to a process.

(there’s also variables of a `protected type` which we’ll ignore for now as they’re another thing altogether)

Tool switches

[@boldport](http://twitter.com/boldport/) asked:

[What are your #FPGA design space exploration techniques?](http://is.gd/BQ66JU)

which he expands upon:

“Design space exploration” is the process of trying out different settings and design methods for achieving better performance. Sometimes the goals are met without any of it — the default settings of the tools are sufficient. When they’re not, what are your techniques to meet your performance goals?

Yet again, the 140 character constraint leaves me with things unspoken….

Version control for FPGAs

[@boldport](http://twitter.com/#!/boldport) recently asked on Twitter what version control software people used on their FPGA designs. I replied that I use [git](http://git-scm.com/) at home and [Subversion](http://subversion.tigris.org/) at work. The reasons why take a bit more than 140 characters, so I’ve written them here!

Inferred state machines in VHDL (vs 2-process-machines of all things!)

A few weeks ago I read a [blog post](http://blogs.msdn.com/b/satnam_singh/archive/2011/02/15/compiling-c-programs-to-fpga-circuits-an-ethernet-packing-processing-example.aspx ) by the illustrious MS researcher Prof. Satnam Singh. He writes about his [Kiwi](http://research.microsoft.com/en-us/people/satnams/) project which he describes as “[trying] to civilise hardware design” – as compared to the explicit writing of state machines.

His example is a Ethernet processor which simply swaps the source and destination MAC addresses over and retransmits them. He has code in C#, and it looks a lot like the inferred state machine style of VHDL I’ve been toying with for a while.

So (finally) I’ve toyed…

Finally, actually reading a PGM file in VHDL

And so, finally, [after all that setup](/node/65), some code [to read PGM files](/node/66/) and [how to make use of it](/node/67/). Next stage will be writing some files!

As always, the code can be [found on github](http://github.com/martinjthompson/image_processing_examples/hdl)