Me: One, Tiny pieces of plastic: Nil

For want of a better place to log how to get at the dishwasher pump *next* time it gets stuck with a tiny piece of plastic blocking the impeller, I’m sticking it here.

In case it helps anyone else it’s a Bosch Classixx (no idea what model no, bought about 2004 IIRC). Here are the steps:

EEWeb electronic design site

I recently became aware of the [EEWeb]( electronic design site (as one of their reps emailed me to see if I’d like my site to appear on their front page… we’ll see if my server can handle that soon!)

It’s sponsored by [Digikey](http://digikeycom/), much like [RS](’s [DesignSpark]( and [Farnell](’s [element14](

There’s an awful lot of content and I’ve barely scratched through a tiny bit of it – worth a trawl!

Variables and signals in VHDL – and when variables are better

VHDL has two types of what-would-normally-be-called-variables:

* `signal`s, which must be used for inter-process communication, and can be used for process-local storage
* `variable`s which are local to a process.

(there’s also variables of a `protected type` which we’ll ignore for now as they’re another thing altogether)

Finally, actually reading a PGM file in VHDL

And so, finally, [after all that setup](/node/65), some code [to read PGM files](/node/66/) and [how to make use of it](/node/67/). Next stage will be writing some files!

As always, the code can be [found on github](

libv – assert_equal, str, etc.

The `assert_equal` functions are part of my library of useful things (maybe this could be a start towards [VHDL’s jQuery]( :) `libv`. Why not just use `assert` as is? Well, it’s useful to report all assert results in the same fashion, particularly to include the values that you expected and what you tested, along with the difference between them – often this is useful debugging information.

Here’s an example….


It’s been very kindly pointed out to me via email (by Tricky) that I was talking complete rubbish saying that [VHDL is rubbish at 2d arrays](/node/60/).

What I should’ve said was “VHDL is rubbish at arrays of other arrays”, which is a subtle but critical difference! Arrays of other arrays are very useful (for example in register files), and the fact that the dimensions of one of the arrays must be known at compile time can make some things tricky to impossible. For example, a generic mux with a variable number of inputs can’t easily also have a generic number of bits on each input.

Reading image files in VHDL

Next up in the image processing series – [reading image files in VHDL](/node/60). This allows our testbenches to operate on real image data. After this we can create a camera model which will produce the pixels and synchronisation signals like a real camera so that we can do complete image tests of a processing pipeline.

Reading image files with VHDL part 1

Please note that this page talks rubbish – [here’s why](/node/62), and [here’s a better version](/node/65).

If we’re going to do some image processing in VHDL, we’re going to need to be able to read images in to our simulations. VHDL’s file handling is pretty poor to say the least, so we’ll keep things simple by only handling a very simple file format – namely [Portable Greymap (PGM)]( And for even more simplicity we’ll handle on one variant with 8-bit pixels (P2 format with Maxval<256).


Inadvertently made the front page of [Hackaday]( with the [solderless drawdio](

Which resulted in an order of magnitude more hits than normal before my server fell over with mysqld leaking its guts all over the console. The youtube [video of it in operation]( that is also linked to from Hackaday has now had 1600+ hits!