When building a large FPGA design, there comes a point when you have to decide where to put the dividing lines between modules. Deciding where to draw the boundaries is a bit of an art.
If you’re a professional (or even proficient amateur) musician, you practise your scales, and other exercises daily. This keeps your muscle-memory alive for the basics of how they will move when playing pieces of real music.
What’s the equivalent for engineers?
This site contains my ramblings on a variety of subjects. No doubt much of it will relate to the design of electronics, especially [FPGA](/taxonomy/term/1)s. There’ll likely be some [music](/taxonomy/term/3) related items and some mention of Linux also.
You can read a bit about me and engineering in my [interview with EEWeb].(http://www.eeweb.com/spotlight/interview-with-martin-thompson)
You can [contact me by email](mailto:firstname.lastname@example.org) if you like.
At primary school, I learned to play recorder (along with most of my generation). I learned by descant and treble recorders, which have slightly different fingerings (or rather the same fingering produces a note which is a fifth higher on one than the other). This stood me in good stead for the clarinet, which I picked up at secondary school – this usees treble recorder type fingering in the “lower register” and descant type fingering in the “upper register”. There’s a few weirdo fingerings in between (sometimes called the “middle register”), but they weren’t hard to pick up. After that I got a tenor saxophone, which made great noises, but was way too loud to practice in the house! So now I play a wind controller…
A couple of times recently, I’ve found myself staring at VHDL code that starts thus:
and had to explain to the author that this is wrong. Yes, using an IEEE-library is *wrong*… how can this be?