A while ago I compared Altera and Xilinx’s ARM-based FPGA combos. More information is now available publicly, so let’s see what we know now…
One thing that’s hard to miss is that Altera are making a big thing of their features to support applications with more taxing reliability and safety requirements.
Altera’s external DRAM interface supports error-checking and correction (ECC) on 32-bit wide memory, whereas Zynq can only do this on 16-bit wide memory, allowing Altera to keep a higher-performance system with ECC. The Altera SoCs also claim ECC on the large blocks of RAM within the processor subsystem (ie the L2 cache and peripheral memory buffers). It appears that Zynq only has parity (ie error checking, but not correction) on the cache and on-chip memory. In Xilinx’s favour, they have performed lots of failure testing (they always have – to a heroic degree!) and the entire processor subsystem has a silent data corruption rate of about 15 FIT. Not seen any FIT data for Altera yet.
Both vendors have memory protection within the microprocessor section to stop errant software processes stomping on each other’s data, but Altera appear to have additional protection within the DDR controller too, which presumably protects against accesses from the FPGA fabric going where they shouldn’t. Again, Zynq does not (as far as I can see) provide this feature.
Looking “mechanically”, Altera have devices which are pinout compatible with and without their many-gigabit-transceiver blocks, which would provide one of my applications with a useful development interface which could be dropped in production without a board respin.
Finally, Altera also have a single-core option. Of course, that only makes any difference if it saves enough money to make the silicon cheaper in any applications which can get away with a single core. Xilinx have clearly decided not… we’ll have to see!