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VHDL

libv has a home

Some of my “useful bits” of library code have lived in `libv.vhd` for a while – I’ve split it off and licensed it with a CC0 license (which means the author disclaims copyright and offers no warranty). It’s [on github](https://github.com/martinjthompson/libv) and I’ll add contributions from anyone who has any!

Either individual functions to add to libv.vhd or great big wodges of useful code (like Jim Lewis’ [randomized testing libraries](http://www.synthworks.com/downloads/index.htm) maybe….)

Should VHDL be extended to allow the use of Unicode

I’m contributing to the [VASG](http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome) group which is working on coming up with what the next revision of VHDL should be able to do.

On today’s conference call, the idea was mooted that VHDL could allow the use of Unicode identifiers (ie entity, signal, variable names etc.).

All of today’s participants were (as far as I recall) native English speakers without much call for accented characters, much less characters from entirely different writing systems. So I’m putting a call out to see if there’s any interest from the wider community in pushing forwards a requirement for VHDL compilers to support Unicode.

Feel free to [mail me](mailto:vhdl_unicode@parallelpoints.com), comment below or [@mention me in a tweet](http://twitter.com/martinjthompson) with your thoughts – I’ll summarise the results here in a few weeks

Tool switches

[@boldport](http://twitter.com/boldport/) asked:

[What are your #FPGA design space exploration techniques?](http://is.gd/BQ66JU)

which he expands upon:


“Design space exploration” is the process of trying out different settings and design methods for achieving better performance. Sometimes the goals are met without any of it — the default settings of the tools are sufficient. When they’re not, what are your techniques to meet your performance goals?

Yet again, the 140 character constraint leaves me with things unspoken….

Inferred state machines in VHDL (vs 2-process-machines of all things!)

A few weeks ago I read a [blog post](http://blogs.msdn.com/b/satnam_singh/archive/2011/02/15/compiling-c-programs-to-fpga-circuits-an-ethernet-packing-processing-example.aspx ) by the illustrious MS researcher Prof. Satnam Singh. He writes about his [Kiwi](http://research.microsoft.com/en-us/people/satnams/) project which he describes as “[trying] to civilise hardware design” – as compared to the explicit writing of state machines.

His example is a Ethernet processor which simply swaps the source and destination MAC addresses over and retransmits them. He has code in C#, and it looks a lot like the inferred state machine style of VHDL I’ve been toying with for a while.

So (finally) I’ve toyed…

Reading image files with VHDL part 3

[Having written a function](/node/66/) to read a PGM image, how do we use it?

Well, the testbench at the bottom of the pgm vhdl file has an example:
[vhdl]
variable i : pixel_array_ptr;
— Without the transpose function, we would have to present the initialisation data in a non-intuitive way.
constant testdata : pixel_array(0 to 7, 0 to 3) := transpose(pixel_array'(
(000, 027, 062, 095, 130, 163, 198, 232),
(000, 000, 000, 000, 000, 000, 000, 000),
(255, 255, 255, 255, 255, 255, 255, 255),

Reading image files with VHDL part 2

Having [set up a library](/node/65/) for reading images, let’s now go on to read an image in!

pgm_read
========

Recall, we have a function:
[vhdl]
impure function pgm_read (filename : string)
return pixel_array_ptr;
[/vhdl]

So, some declarations – fairly self-explanatory:
[vhdl]
file pgmfile : text;
variable width, height : coordinate; — storage for image dimensions
variable l : line; — buffer for a line of text
variable s : string(1 to 2); — to check the P2 header

Reading image files with VHDL part 1 (again)

Data storage
============
One things VHDL can do ([contrary to popular belief :)](/node/60/)) is 2-D arrays. So reading images into a 2-D array is a very natural way to store the data.

We’ll create a package called `pgm` to keep all our image reading and writing code together:

[vhdl]
package pgm is
subtype coordinate : natural;
subtype pixel is integer range 0 to 255;
type pixel_array is array (coordinate range <>, coordinate range <>) of pixel;
type pixel_array_ptr is access pixel_array;
— Function: transpose

Numbers in VHDL

A couple of times recently, I’ve found myself staring at VHDL code that starts thus:


library ieee;
use ieee.std_logic_arith.all;

and had to explain to the author that this is wrong. Yes, using an IEEE-library is *wrong*… how can this be?