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Testing

Image processing series

I’ve begun a series of articles showing the stages of development of an image processing system. The aim is to go through from describing algorithms at a very high level in Scilab, making tradeoffs in implementation ideas, before describing the system in VHDL and comparing the results.

[Part 1 – edge detection](/node/46) is now up…

Making things easy

Yet again, Altera make it easy (and cheap – $49!) for people to [play](http://www.altera.com/b/bemicro-sdk.html?WT.mc_id=nm_so_tw_xx_tx_t_371) with their tools:

Altera dev boardAltera’s USB development board

FPGAs and floating point

Altera’s newest DSP block is quite clearly designed to deal with [double-precision](http://en.wikipedia.org/wiki/Double_precision_floating-point_format) floating-point numbers from the start. They are betting (quite rightly IMHO) that the future is going to move away from pure fixed-point implementations.

How much hierarchy do I need?

When building a large FPGA design, there comes a point when you have to decide where to put the dividing lines between modules. Deciding where to draw the boundaries is a bit of an art.