Variables and signals in VHDL – and when variables are better

VHDL has two types of what-would-normally-be-called-variables:

* `signal`s, which must be used for inter-process communication, and can be used for process-local storage
* `variable`s which are local to a process.

(there’s also variables of a `protected type` which we’ll ignore for now as they’re another thing altogether)

Tool switches

[@boldport](http://twitter.com/boldport/) asked:

[What are your #FPGA design space exploration techniques?](http://is.gd/BQ66JU)

which he expands upon:


“Design space exploration” is the process of trying out different settings and design methods for achieving better performance. Sometimes the goals are met without any of it — the default settings of the tools are sufficient. When they’re not, what are your techniques to meet your performance goals?

Yet again, the 140 character constraint leaves me with things unspoken….